I have recently dived into the world of FPGA, via the purchase of the Avnet Spartan-3A Evaluation Kit priced a rather marvelous $49.
For those of you who are interested in diving into this as well, I highly recommend that you do not use Avnet's Avprog software to program the device, it is terrible. I've had pretty good success running Xilinx's Webpack ISE dev environment on linux (Ubuntu 9.10) using ASTriAEKiPro to program the SPI flash on the board.
My first project? A while ago I was digging into the schematics of the Vox Continental Organ (think: The Doors / Light my Fire), in an attempt to see how it would be possible to produce something similar using modern components.
thanks to combo organ heaven for the images
In this image you can see the guts of this monster. Above the keys, you can see there are 12 identical boards in a row. These are the tone generators, and their operation is quite simple.
The boards consist of a LC oscillator producing a square wave. For each of the 12 boards this oscillator is generating a square wave for the each musical note (i.e C, C# ... B), which you can see to the left of the board shown here. The repeated sections you see going right are the frequency dividers that take this top frequency and divide the frequency in half to get the same note one octave lower, and then another divider divides that in half, and another divides that, and another.. 6 times. This gives us 6 octaves for each note. Each key on the keyboard has a number of switches which routes one of these signals onto a number of audio busses, the volume of which is controlled by the distinctive organ drawbars.
Later on, transistor organs replaced these components with ICs. There was one IC called a "Top Octave Generator" which, when given a ~2mhz clock generated the top frequencies for the musical notes by dividing this clock by some constants:
C -> 239
B -> 253
A# -> 268
A -> 284
G# -> 301
G -> 319
F# -> 338
F -> 358
E -> 379
D# -> 402
D -> 426
C# -> 451
These where then fed into a clock divider IC to generate the rest of the notes. These clock dividers are simply binary counters.
My initial (non-fpga) design, involved using 12 PIC 12F683 ICs to generate the top musical frequencies. This ICs have a fairly good and stable internal oscillator and the code to divide this by a certain number is fairly trivial. Instead of using the internal timer to do generate this wave, I just used a big block of NOPs that delayed the amount of time needed in between each flip of the square wave, and i generated the right number of NOPs from a script. I then took this musical square wave from the PIC and fed it into a CMOS 4024 7bit counter IC. This gave me pretty usable results.
The only thing left to do was to program 12 PICs with 12 individual timing programs, connect them to 12 4024 counters, and then begin the giant wiring bundle to make it work (each key would need to fire 4 tones, there's 61 keys...)
It was at that point that I stopped working on this project.
However, it suddenly occurs to me that an FPGA could easily perform the function of those 24 chips. I can quite easily divide the 16mhz clock on this fpga board into 2mhz, and I can quite easily divide that into 12 seperate musical square waves, and i can very easily divide those 12 square waves into several octave square waves. The real big issue with this board is the number of user IO pins available, which is about 40+, which is not enough tones. The vox continental had 12 divider cards with 6 octaves each, thats 12 * 6 = 72 individual square waves, and therefore I'd need 72 pins of user IO. I could fix this by having the board only output the 12 top octaves and then use the cmos divider chips again, but that kind of defeats the point, having an fpga generate 12 square waves is pretty much overkill.
However, since this is just a starter project to cut my teeth on fpga, I decide I'm just going to have the fpga output 3 octaves per note, which is 36 tones as a proof of concept. One day, If I decide to build the full on organ and undertake the massive wiring project, I can easily obtain an FPGA that has the right number of IO pins.
After this, I suppose I will have the write the obligatory FPGA pong program.