Organ FPGA First version (Simulated)

Here it is, the first version of the code. I tried to use a BUFG to buffer the 2mhz clock I'm generating for the clock dividers, but for some reason Xilinix ISim didn't seem to want to simulate it (I was probably doing it wrong.)

`timescale 1ns / 1ps

module clk2freq(
    input clk2mhz,
    output [4:0] notes
    );
 parameter ctarget = 239;
 reg [10:0] ctr;
 reg [4:0] out;
 initial ctr = 0;
 initial out = 0;
 assign notes[4:0] = out[4:0];

 always @(posedge clk2mhz) begin
   ctr = ctr + 1;
   if (ctr == ctarget) begin
    ctr = 0;
    out = out + 1;
   end
 end
endmodule


module main_clk_div(
    input clk,
    output mhz2
    );
 
 reg  [3:0] div_clk;
 initial div_clk = 0;
 assign mhz2 = div_clk[2];
 
 always @(posedge clk) begin
  div_clk = div_clk + 1;
 end
endmodule

module organ(
 input clk16,
 output [4:0] c_notes,

 output [4:0] cs_notes,

 output [4:0] d_notes,

 output [4:0] ds_notes,

 output [4:0] e_notes,

 output [4:0] f_notes,

 output [4:0] fs_notes,

 output [4:0] g_notes,

 output [4:0] gs_notes,

 output [4:0] a_notes,

 output [4:0] as_notes,

 output [4:0] b_notes
 );

   
 // create a 2mhz clock generator
 wire  clock2mhz;
 main_clk_div main_clock_gen(clk16, clock2mhz);


 clk2freq #(239) c_generator (clock2mhz, c_notes);

 clk2freq #(253) b_generator (clock2mhz, b_notes);

 clk2freq #(268) as_generator (clock2mhz, as_notes);

 clk2freq #(284) a_generator (clock2mhz, a_notes);

 clk2freq #(301) gs_generator (clock2mhz, gs_notes);

 clk2freq #(319) g_generator (clock2mhz, g_notes);

 clk2freq #(338) fs_generator (clock2mhz, fs_notes);

 clk2freq #(358) f_generator (clock2mhz, f_notes);

 clk2freq #(379) e_generator (clock2mhz, e_notes);

 clk2freq #(402) ds_generator (clock2mhz, ds_notes);

 clk2freq #(426) d_generator (clock2mhz, d_notes);

 clk2freq #(451) cs_generator (clock2mhz, cs_notes);

     
endmodule
 

What's next? Route all the signals to IO pins and test this sucker.